The present invention relates to circuits integrating a power MOS transistor with its control circuit, and more particularly to a control circuit with load detection for a high-frequency switching power MOS transistor.
FIG. 1 very schematically shows a conventional example of an integrated circuit of the type to which the present relates. Integrated circuit 1 essentially includes a power MOS transistor 2, the drain d and the source s of which define terminals, respectively 3 and 4 of the integrated circuit in communication with the outside. Terminal 3 corresponds to a terminal on which a voltage for supplying the load controlled by circuit 1 is applied. Terminal 4 corresponds to an output terminal intended for connection to a first terminal of the load to be controlled, the other terminal of the load being generally grounded. Transistor 2 is controlled by a circuit 5 (CTRL), an output terminal of which is connected to gate g of transistor 2. Circuit 5 generally includes several input terminals (symbolized by a multiple-wire connection 6) and/or terminals for parameterizing the circuit operation.
Most often, in the use of a circuit 1 such as illustrated in FIG. 1, it is also desired to detect the presence of the load in the circuit. For this purpose, circuit 1 further includes a terminal 7 intended for providing the result of a load presence detection performed within circuit 1 by a block 8 (DET).
FIG. 2 shows, in the form of block diagrams, an example of assembly of an integrated circuit 1 such as illustrated in FIG. 1 to control a load 10 (Q). Load 10 is series-connected with transistor 2 (not shown in FIG. 2) of circuit 1, that is, terminal 3 is connected to a positive supply terminal for application of a voltage Vbat, and terminal 4 is connected to a first terminal of load 10, a second terminal of which is connected to ground m. In the example of FIG. 2, the assembly provides the function of detecting the presence of the load between terminals 4 and m. The present invention more specifically applies to the load detection and, more precisely, to the detection of the presence of the unsupplied load (that is, with transistor 2 in the off state).
To detect the presence of a load 10 in the assembly while said load is not supplied, a resistor Rp is provided in parallel with transistor 2. In other words, resistor Rp is connected, most often externally to circuit 1, between terminals 3 and 4. With such an assembly, if the load is present, terminal 4 is at a potential corresponding to the ground when transistor 2 is on. If the load is absent, that is, terminal 4 is floating, this terminal is at a positive potential, here potential Vbat, minus the voltage drop in resistor Rp. The value of resistor Rp generally is several kilo-ohms to avoid generating too high a consumption or strongly dissipating.
Generally, and especially if the value of voltage Vbat is different from the low supply voltage of detection circuit 8, resistor Rp is connected between terminal 4 and a terminal (not shown) of application of a biasing voltage Vpol (for example, 5 volts).
Exploiting the measurement of the voltage on terminal 4 by resistor Rp raises several problems.
A first problem is due to the switching time of transistor 2. This problem is illustrated by FIG. 3A, which shows in the form of a timing diagram an example of the shape of the output voltage V4 of circuit 1 for supplying a load Q.
This example relates to a turn-on control at a time t0 that translates as a voltage V4 reaching voltage level Vbat (neglecting the series voltage drop in transistor 2 in the on state) at a time t1. The difference between times t0 and t1 represents the turn-on switching time of transistor 2. In the example of FIG. 3A, it is assumed that at a time t2, circuit 5 turns off transistor 2. This turn-off control translates, from a time t3, as a decrease of voltage V4 until said voltage is annulled at a time t4. The time interval between times t2 and t3 corresponds to the response time (tdoff) of the transistor, that is, the delay of its switching with respect to the received control signal. The time interval between times t3 and t4 corresponds to the off time of the transistor (tf), generally given as being the time of decrease of the voltage on terminal 4 from 90% to 10% of voltage Vbat.
The detection of the presence of a load in series with transistor 2 can, in the off state, be polluted by the off switching time of the transistor. Indeed, in exploiting the measurement of the potential of source s of transistor 2 between times t2 and t4, the absence of a load will be detected, even if said load is present. This is due to the fact that the off state of the transistor is detected from time t2 when the control circuit has sent the turnoff order, but that the disappearing of the potential on terminal 4 when a load is present only occurs at the end of the switching time.
Accordingly, the exploitation of the measurement has to be delayed with respect to time t2 of the turn-off control. This delay is most often performed by a capacitive filter. The filtering time must then be adapted to the transistor switching time.
Another problem that is raised in exploiting this voltage detection to determine the presence or the absence of a load while the circuit is off is that the transistor switching time depends on supply voltage Vbat of the assembly. Accordingly, a filtering time corresponding to the worst possible case of the assembly has to be provided. This situation is illustrated in FIG. 3B that illustrates, in the form of timing diagrams, the shape of a signal for controlling the exploitation of the measurement. This signal illustrates the necessary filtering delay. In the example of FIGS. 3A and 3B, it is assumed that as long as control signal Vf illustrated in FIG. 3B is high, the reading of the measurement voltage cannot be performed. Accordingly, this signal is high during the entire period (t0-t2) when the transistor is on, since the presence of the load is then detected by other means (current measurement), and between time t2 and a time t5 representing the necessary filtering delay after the transistor turn-off order. As illustrated in FIG. 3B, it is generally necessary, to guarantee a proper detection, to take a filtering delay (t2-t5) greater than the minimum filtering delay (times t2 to t6) itself corresponding to the worst off switching case of transistor 2 (illustrated by the dotted lines in FIG. 3A).
All these precautions often result in extended filtering times that, in some applications, even prevent the detection of the absence of a load. Such is the case, for example, if integrated circuit 1 is used to control transistor 2 at frequencies on the order of one kilohertz, which is a usual value in pulse-width modulation applications (PWM). In such applications, the absence of a load can then no longer be detected since the security margin to be taken on the filtering delay is not negligible, or may even exceed the period of the signal controlling the transistor to the on state.
The disclosed embodiments of the present invention provide a novel circuit for detecting the presence of a load that overcomes the disadvantages of known circuits and enables reliable detection of the presence of a load.
While a first solution would be to reduce the switching time of the circuit power transistor, such a solution would not be fully satisfactory, since reducing the switching time of a power MOS transistor inevitably results in increasing the switching noise. Accordingly, this solution generates a noise problem, which is most often not desirable.
The present invention thus also provides a solution that is compatible with the other circuit operation requirements and, in particular, with a need for low switching noise.
The present invention provides reducing the filtering time to the smallest possible value. For this purpose, the present invention provides making the filtering time self-adaptive according to the circuit supply voltage.
More specifically, the present invention provides an integrated circuit for controlling a power MOS transistor, including a circuit for detecting the presence of an external load, using filtering means for delaying a time of taking the detection into account with respect to the occurrence of a turn-on control signal of the power transistor, and means for controlling the filtering time with the switching time of the power transistor.
According to an embodiment of the present invention, where the switching times of the power transistor can be parameterized by the charge/discharge of a first capacitor by a first constant current source, said filtering means include a second constant current source for discharging a filtering capacitor, the value of the constant current of the second source being proportional to the value of the constant current of the first source.
According to an embodiment of the present invention, the circuit includes means for making a voltage of precharge of the second capacitor proportional to the initial or final voltage across the first capacitor upon switching of the power transistor.
The present invention also provides a method for detecting the presence of a load in series with a power transistor integrated with its control circuit, consisting of making a filtering time of detection of the output voltage of the integrated circuit dependent on the switching time of the power transistor.
According to an embodiment of the present invention, the method consists of controlling the discharge current of a filtering capacitor with the value of a charge current of a capacitor for parameterizing the switching time of the power transistor, and of making the precharge voltage of the filtering capacitor proportional to the integrated circuit supply voltage.
The present invention further relates to a circuit for detecting the presence of a load in series with a power transistor integrated with its control circuit, this detection circuit including a filtering cell adapted to controlling the time of taking the detection into account with the switching time of the power transistor.
According to an embodiment of the present invention, said filtering cell includes a capacitor associated with a current source adapted to discharging the capacitor under a constant current, this constant current being made proportional to a constant current determining the switching time of the transistor.
According to an embodiment of the present invention, the detection circuit includes means for determining a minimum filtering time.
According to an embodiment of the present invention, said filtering cell includes a resistive dividing bridge connected in parallel with the external load, the midpoint of the dividing bridge being connected, via a diode, to a first terminal of the filtering capacitor connected on an input terminal of an inverter, the output terminal of which provides the result of the detection, a second terminal of the filtering capacitor being grounded.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.